Communication receivers that recover digital signals must sample an analog waveform and then reliably detect the sampled data. Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. As data rates increase, the receiver must both equalize the channel, to compensate for such corruptions, and detect the encoded signals at increasingly higher clock rates. Decision-feedback equalization (DFE) is a widely used technique for removing intersymbol interference and other noise at high data rates.
Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously recovered (or decided) data. In one typical DFE-based receiver implementation, a received analog signal is sampled in response to a data-sampling clock after DFE correction and compared to one or more thresholds to generate the recovered data.
To acquire the correct clock phase and properly sample incoming data signals in the center of the data “eye” opening, a clock and data recovery (CDR) circuit derives the correct clock phase by “locking” onto transitions in the incoming data signals. However, because of linear and non-linear distortions in the receiver, transmitter, or channel circuitry, the transitions might vary in phase with respect to the center of the eye depending upon the transition polarity (e.g., positive going or negative going). By relying on a single transition per clock eye for recovering clock phase might result in the introduction of considerable error in the data-sampling clock phase and lead to errors by the receiver.